The invention relates to a dual-port memory cell in accordance with the preamble of claim 1, as disclosed in U.S. Pat. No. 5,010,519 or in U.S. Pat. No. 4,292,677.
The invention likewise relates to a DRAM semiconductor memory having dual-port memory cells.
Dual-port memory cells is a term designating all memory cells which have precisely two data lines, A dual-port memory cell designed as a static memory cell (static random access memory; SRAM) typically contains eight transistors, in each case four selection transistors (transfer gates) and four memory transistors (inverters). These transistors are each connected to two word lines (selection lines) and to two bit lines (data lines). Dynamic dual-port memory cells (dynamic random access memory; DRAM) have not been known heretofore.
Future microelectronic circuits will realize complicated memory architectures with numbers of transistors ranging from 1012 to 1015. An elementary boundary condition for economic reasons is undoubtedly ascribed here to the smallest possible area outlay of each of the memory cells on the semiconductor chip. The total number of transistors of an, individual memory cell and the wiring outlay thereof, in which predetermined xe2x80x9cdesign rulesxe2x80x9d have to be taken into account, essentially determines the size of the memory cell and, consequently, the area outlay of the semiconductor memory constructed from a multiplicity of memory cells of this type.
A further very important boundary condition, which plays a very important part in particular for the semiconductor memory containing the memory cells, results from the requirement of the shortest possible access time to the individual memory cells of the semiconductor memory. Shortening the effective access time is very important in particular in the case of the fundamentally very slow dynamic memories (DRAMs), access time to the individual memory cells of the semiconductor memory. Shortening the effective access time is very important in particular in the case of the fundamentally very slow dynamic memories (DRAMs), in order not to give rise to an excessively large difference with regard to the clock rates of the processors used as standard nowadays. The access time in a semiconductor memory essentially results from the propagation time of the data signals on the word lines and from the charge reversal of the storage capacitances. However, since the effective interconnect length increases by about 40% in the case of a semiconductor memory transition from one-port memory cells to two-port memory cells, the undesirable result is a corresponding increase in the signal propagation times and, consequently, an increase in the access times. This causes additional parasitic capacitances and resistances in the word lines and data lines, and because of these the signal change times and, consequently, the access times to the individual memory cells are considerably prolonged.
The present invention is therefore based on the object of specifying a dynamic dual-port memory cell with a space-sating design.
According to the invention, this object is achieved by means of a dual-port memory cell having the features of patent claim 1.
In the preferred configuration, the dual-port memory cell according to the invention in each case has a capacitive element designed as a memory transistor and two selection transistors, whose load paths are connected in series and this series circuit is arranged between two data lines. This arrangement makes it possible for a dual-port memory cell to be read from and written to in parallel by two date processing units.
It would also be conceivable, of course, to realize the capacitive element as two capacitors which are short-circuited together and are in each case arranged between the center tap of the selection transistors and a reference-ground potential. DRAM memory cells, in particular on account of their comparatively small capacitances and short respective line lengths, are particularly advantageous in dynamic semiconductor memories since here the corresponding memory cells can be given very small dimensions.
The decisive advantage of the dual-port memory cells according to the invention in a DRAM memory architecture resides, as already mentioned, in an area-optimized design, that is to say in the possibility of providing a memory architecture having a distinctly reduced area outlay. In particular when the capacitive a element is designed as a CMOS transistor, each of the load path terminals of the CMOS transistor can be short-circuited with a respective load path terminal of the selection transistors. It is particularly advantageous here when the terminal nodes of the CMOS transistors coincide with the terminal nodes of the selection transistors. By virtue of this saving of area-intensive terminal nodes, the dual-port memory cell according to the invention manages with a very small area requirement, as a result of which dual-port DRAM memory cells can thus be fabricated particularly cost-effectively. However, the saving of terminal nodes can also advantageously be realized with capacitive elements designed as capacitors.
In the memory cell according to the invention, both output paths of the capacitive element have a defined potential of approximately the same magnitude.
Functionality of this type has not been able to be ensured hitherto in conventional DRAM memory cells since here a respective terminal of the capacitive element always xe2x80x9cfloatsxe2x80x9d, i.e. is at an undefined potential. DRAM memory cells have therefore had to be recharged at regular intervals (refresh operation). During this refresh operation, it has not been possible to read from or write to the DRAM memory cell, as a result of which undefined switching states can never be completely avoided. Therefore, this abovementioned functionality has been achievable hitherto only by SRAM memory cells. The dual-port DRAM memory cell according to the invention makes it possible to combine the above-described advantages of a DRAM memory cell, i.e. shorter access time, area optimization, etc., with the functionality of an SRAM memory cell with regard to the defined switching states thereof.
On account of its design, i.e. on account of the small number of circuit elements and short interconnect lengths, the memory cell according to the invention is, moreover, highly insensitive to noise. The memory cell therefore exhibits a distinctly improved signal-to-noise ratio (SNR) in comparison with convention dual-port memory cells.
The smaller number of transistors and the short effective interconnect lengths additionally bring about very short access times. Moreover, the access time is additionally improved on account of in the reduced parasitic capacitances and resistances in the critical line path. As a result, it is possible to provide memory systems which have a higher performance for the same clock frequency.
In particular, the invention is particularly advantageously suitable for xe2x80x9cmulti-port semiconductor memoriesxe2x80x9d having a multiplicity of dual-port DRAM memory cells according to the invention.
The subclaims are directed as preferred configurations and developments of the invention.